IEEE Edge AI Hackathon 2026
Organizers & Partners:
- Organizers: IEEE Electron Devices Society PMEC SBC, IEEE Council on Electronic Design Automation (CEDA), and Dept. of Electronics & Telecommunication Engineering, PMEC
- Hosting Partner: Unstop
- Principal Sponsor: AMD
- Technical Sponsors: Renesas & Microchip
- Sponsors: IEEE Bhubaneswar Section, Chips to Startup (C2S), ETIOS Society
Track Winners & Results
Heartiest congratulations to the triumphant teams who engineered state-of-the-art edge AI solutions across our three official hardware tracks.
Track 1: FPGA Acceleration
Track 2: Raspberry Pi / Renesas
Track 3: ESP32 / Arduino TinyML
Esteemed Leadership, Judges & Organizers
Guided by visionary leadership from PMEC, IEEE Electron Devices Society, and prominent industry evaluation panel.
Esteemed Judges with Principal, PMEC
Distinguished industry mentors, evaluation jury members, faculty coordinators, and the Principal of Parala Maharaja Engineering College during the final round evaluation and valedictory ceremony.
Organizers & Student Branch Volunteers
The dedicated student executive committee, department volunteers, and technical leads of IEEE EDS PMEC Student Branch Chapter who spearheaded the 21-hour hardware event seamlessly.
Event Gallery
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Sponsored by Renesas Electronics
NEW WINNER REWARD!
Renesas QuickConnect Beginners Kit V2.0
MORE THAN A TROPHY. TAKE HOME THE HARDWARE.
The winning team of each official hackathon track will receive a dedicated Renesas QuickConnect Beginners Kit V2.0 hardware kit — empowering your team with same hardware for bigger possibilities.
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Explore the Renesas MCU ecosystem
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Build real-world embedded solutions
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Take your Edge AI ideas further
42 TEAMS SELECTED FOR THE FINAL ROUND
37 initial finalists + 5 additional teams selected after the 2nd Round Evaluation.
Search the complete list of 42 teams below by Team Name, Team Leader, or Institution.
FINAL ROUND TEAMS
37 Initial Finalists + 5 Selected after 2nd Round Evaluation
FINAL ROUND STRUCTURE
Round 1 (Simulation) & Round 2 (Hardware Evaluation)
TOTAL PRIZE POOL
Merit awards, sponsor hardware kits & certificates
| Team Name | Team Leader | Institution |
|---|---|---|
|
AcousticMinds
|
Abaan Ansari
|
D.Y. Patil College of Engineering, Akurdi, Maharashtra
|
|
alt_chip
|
Subhash Gautham G
|
Saveetha Engineering College, Chennai
|
|
Angrybirds
|
Aman Behera
|
NIST University, Berhmapur, Odisha
|
|
Auctrix
|
Ann Theressa Babu
|
Model Engineering College, Kochi, Kerala
|
|
Chip Forgers
|
S Rupendra
|
National Institute of Technology, Calicut
|
|
CocoMat
|
Shibani Pradhan
|
Parala Maharaja Engineering College, Berhmapur, Odisha
|
|
Code Cortex
|
P Nikita
|
Parala Maharaja Engineering College, Berhmapur, Odisha
|
|
Core4
|
Smrutirekha Tripathy
|
Khallikote Unitary University, Berhampur, Odisha
|
|
CoreSentinel
|
Divyansh Tripathi
|
NIT Rourkela
|
|
Critical Condition
|
Vinay Kumbar
|
KLS Gogte Institute of Technology, Belagavi, Karnataka
|
|
EdgeNova
|
Samala Bhavani
|
B. V. Raju Institute of Technology, Narsapur, Telangana
|
|
HACKX-V
|
Sachidananda Mallick
|
Biju Patnaik University Of Technology, Rourkela, Odisha
|
|
LUMEN
|
Shaik Khadar Vali
|
Siddhartha Academy Of Higher Education,Vijayawada, Andhra Pradesh
|
|
Lumen Ai
|
Gaurav
|
IIT Patna
|
|
Natraj AI
|
Punit Gaur
|
Engineering College Ajmer, Rajasthan
|
|
Neuro Sense
|
Prerana Punyakankshi
|
Odisha University of Technology and Research, Bhubaneswar, Odisha
|
|
Neurofabric
|
Madesh P B
|
Bannari Amman Institute of Technology, Chennai
|
|
NEXT IN
|
Adarsh Swarup Maharana
|
Parala Maharaja Engineering College, Berhmapur, Odisha
|
|
NovaEdge
|
Shivu jagruth R
|
RV College of engineering, Bengaluru, Karnataka
|
|
Quantum coders
|
Vivek Kumar Gupta
|
Parala Maharaja Engineering College, Berhmapur, Odisha
|
|
S.py
|
Rahul Sharma
|
National Institute of Technology, Raipur
|
|
SentiShot
|
Katta Bhuvan
|
Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology
|
|
SENTRA
|
Dinesh S
|
Chennai Institute Of Technology, Tamil Nadu
|
|
SpectrumSeeker
|
Tanishk Raj
|
IIT Patna
|
|
Systolic Squad
|
Akash B
|
PSG institute of technology and applied research, Coimbatore, Tamil Nadu
|
|
Team "Haaassh"
|
Sindhuripa Mishra
|
Parala Maharaja Engineering College, Berhmapur, Odisha
|
|
Team DIAT
|
Sayana Bharati
|
Defence Institute of Advanced Technology, Pune, Maharashtra
|
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Team Perceptrons
|
Atreya Mohanty
|
Kalinga Institute of Industrial Technology, Bhubaneswar, Odisha
|
|
Team Sutra-dhar
|
Keerti S Kallur
|
KLE Technological University BVB Campus, Hubli, Karnataka
|
|
TeamNova
|
Rithika S
|
Bannari Amman Institute Of Technology, Tamil Nadu
|
|
TECHBALLERS
|
Hitesh K P
|
Chennai Institute of Technology, Chennai, Tamil Nadu
|
|
UnifiedUnits
|
Roshini R
|
Bannari amman Institute of Technology, Tamil Nadu
|
|
Vector Aid
|
Prince Andrew A
|
Saveetha Engineering College, Chennai
|
|
VMACers
|
Shaurya Pratap Singh
|
IIT Guwahati
|
|
Voxtacit
|
D Sameer
|
Sri Venkateswara College of Engineering, Tirupati
|
|
WIN
|
Aman Gupta
|
SVNIT, Surat
|
|
ZEROSDC
|
Dablu Biswakarma
|
Biju Patnaik University Of Technology, Rourkela, Odisha
|
|
XCaliber
⚡ 2ND ROUND
|
M. Tarun
|
NIST University
|
|
Team Electro
⚡ 2ND ROUND
|
Sanjib Kumar Panda
|
Odisha University of Technology and Research
|
|
VISTA
⚡ 2ND ROUND
|
Gajula Varun
|
B. V. Raju Institute of Technology, Narsapur
|
|
TEAM ELECTRO
⚡ 2ND ROUND
|
Ramakrishnan K
|
SRM Easwari Engineering College
|
|
Team Rocket
⚡ 2ND ROUND
|
Bibek Kumar Sahu
|
NIST University
|
Event Information
| Event Name: | Edge AI Hackathon 2026 |
| Status: | Finalist Teams Announced |
| Current Stage: | Round 1 – Software Simulation (Online) |
| Result Announcement: | 18 September 2026 Announced |
| Finals Confirmation: | 23 September 2026 (Finalist Teams) |
| Mode: | Online (R1) / Onsite at PMEC (R2) |
| Venue: | Parala Maharaja Engineering College, Berhampur, Odisha |
| Finals Dates: | 4th, 5th, 6th October, 2026 |
| Final Registration: | Shared via Email (Finalists) |
About the Hackathon
The Edge AI Hackathon 2026 is an elite hardware-centric sprint designed to foster local engineering innovation. Participating teams will work under time constraints to address real-world application challenges, creating optimized hardware solutions that utilize embedded intelligence at the sensor node.
By combining FPGA, microcontrollers, and low-latency computer logic, students are encouraged to bridge the gap between high-level algorithms and resource-constrained silicon platforms.
Major Focus Themes:
About Parala Maharaja Engineering College (PMEC)
Parala Maharaja Engineering College (PMEC), Berhampur came into existence in the year 2009 on April 26th, with an area of nearly 80 acres. Now this college acts as an Autonomous college affiliated to BPUT, Odisha, from the year 2021. This college is one of the premier technical institutes in the state and is the only Government Engineering College in South Odisha. It offers 8 B.Tech programmes, 5 M.Tech programmes, and serves as a Nodal Centre for Ph.D. research under BPUT.
Government of Odisha has recognized PMEC as a leading institution with state-of-the-art academic infrastructure, laboratories, library, hostels, research facilities and continuous campus development.
Department of Electronics & Telecommunication Engineering
The Department of Electronics and Telecommunication Engineering was established in 2013 with an intake of 60 students. The department has expertise in Communication Systems, Image Processing, Signal Processing, VLSI Design and Embedded Systems.
Students receive extensive laboratory exposure through modern facilities and project-based learning. The department has received ₹65.19 Lakhs under the Chips-to-Startup (C2S) scheme from MeitY, Government of India, enabling the establishment of advanced laboratories equipped with industry-standard FPGA boards and EDA software. Graduates pursue successful careers in both core electronics and IT industries.
Chips to Startup (C2S) Programme
National Semiconductor Initiative • Ministry of Electronics & Information Technology (MeitY) • Government of India
Parala Maharaja Engineering College (PMEC) is proudly selected under the national C2S Programme to foster indigenous chip design capabilities.
About C2S
A national initiative by MeitY to catalyze the domestic semiconductor ecosystem. The programme empowers engineering institutions with advanced training in Chip Design, FPGA, ASIC, and SoC development. Supported by a ₹65.19 lakh grant, PMEC bridges theoretical VLSI concepts with real-world silicon innovation through the state-of-the-art EDCSD Laboratory.
PMEC's Indigenous Chip
IC-C2S0061
A High-Performance Multiplier IC designed entirely by researchers at PMEC and presented under the national C2S Programme. Fabricated through SCL Chandigarh, it stands as one of India's indigenous semiconductor chips powering modern hardware applications.
IEEE Community at PMEC
A growing ecosystem of IEEE student professionals, researchers, and innovators at Parala Maharaja Engineering College
IEEE Student Branch PMEC
Established in November 2024, the IEEE Student Branch at PMEC is one of the fastest-growing student communities in Odisha, promoting innovation through workshops, competitions, technical talks, and industry interaction.
IEEE Electron Devices Society PMEC SBC
Established in April 2026, the IEEE EDS Student Branch Chapter focuses on semiconductor devices, VLSI, embedded systems, Edge AI, and hardware innovation through research, hackathons, and technical activities.
IEEE Council on Electronic Design Automation
The IEEE CEDA chapter promotes Electronic Design Automation, FPGA, ASIC, SoC design, and hardware innovation while supporting the Chips to Startup (C2S) ecosystem at PMEC.
Faculty Leadership
Dr. Raghunandan Swain
Providing academic leadership and research guidance to the IEEE EDS PMEC Student Branch Chapter, fostering innovation in semiconductor devices, VLSI, and embedded systems.
View Profile
Dr. Suryalok Dash
Mentoring IEEE student activities and fostering professional growth through technical and leadership initiatives across the IEEE Student Branch and EDS Chapter.
View ProfileWhy Build at PMEC?
Unlocking potential through state-of-the-art silicon design labs and advanced embedded systems platforms
Advanced FPGA Laboratory
Access high-end AMD/Xilinx FPGA boards for real-time parallel computing and custom logic hardware design.
Industry Standard EDA Tools
Train on professional Electronic Design Automation software suites for schematic entry, circuit simulation, and layout design.
Renesas & AMD Hardware
Prototype on modern Edge AI hardware platforms, including Renesas microcontrollers and AMD system-on-chips.
Embedded Systems Development
Deploy low-power algorithms onto ARM Cortex and RISC-V development architectures using multi-sensor interfaces.
C2S Semiconductor Laboratory
Leverage the MeitY-backed Chips-to-Startup laboratory ecosystem designed specifically for microelectronics and chip design.
Research Driven Environment
Collaborate under academic mentors specializing in VLSI circuits, machine learning acceleration, and smart sensor nodes.
Supported Hardware Platforms
Explore the diverse suite of FPGA, microcontroller, and edge compute platforms available to hackathon teams
Microchip
Microchip PolarFire SoC Discovery Kit
Features a multi-core RISC-V Linux-capable processor subsystem integrated with a low-power PolarFire FPGA fabric, ideal for real-time Edge AI vision, signal processing, and low-latency hardware acceleration.
- Quad-core 64-bit RV64GC RISC-V CPU
- 95K Low-power Logic Elements
- Linux OS & Bare-metal Support
AMD
AMD / Xilinx FPGA Development Boards
High-throughput FPGA architectures engineered for custom hardware logic synthesis, DSP arithmetic pipelines, high-speed interfaces, and parallel matrix compute acceleration.
- High-density DSP slices & Block RAM
- Vivado ML EDA Toolchain suite
- Real-time parallel algorithmic pipelining
Renesas
Renesas Edge AI Development Kits
Ultra-low power, security-enabled microcontroller evaluation boards tailored for deploying machine learning inference models at the sensor edge with energy efficiency.
- Hardware-accelerated neural compute units
- Flexible Software Package (FSP)
- Low-power deep sleep operating modes
Raspberry Pi 4 / 5 Compute Platforms
Versatile embedded Linux single-board computers optimized for real-time video analytics, sensor hub fusion, Python/TensorFlow Lite deployment, and edge gateway solutions.
- TensorFlow Lite / ONNX / OpenCV
- CSI Camera & multi-sensor buses
- High-speed Gigabit networking
ESP32 Intelligent Embedded Modules
Cost-effective, highly integrated Wi-Fi and Bluetooth SoC modules engineered for TinyML applications, edge telemetry, distributed sensor networks, and low-power control.
- TinyML & Edge Impulse integration
- Ultra-low sleep current operations
- Wireless mesh & cloud connectivity
HACKATHON SCHEDULE
IEEE EDGE AI HACKATHON 2026 • 04–06 OCTOBER 2026 • PMEC, Berhampur, Odisha
Desk Registration starts
- Team & member verification
Desk Registration
- Goodies & ID card collection
Lunch
Lunch break for participants and mentors at the campus dining hall.
Formal Inauguration and Hackathon Begins
- Software design, development & implementation on the development board
Dinner
Dinner served for hackathon teams at PMEC campus.
Breakfast
Morning breakfast served at the campus dining hall.
Design & Implementation
- Software development, hardware–software integration, testing and development
Lunch
Lunch break for participants.
Evaluation - 1
- 1st round evaluation and On-Site Challenge
Dinner
Dinner served at the venue.
Breakfast
Morning breakfast for participants.
Final Preparation
- Testing, debugging and final demonstration preparation
Evaluation - 2
- 2nd round evaluation of Track – 2 and Track – 3 teams
Lunch
Lunch break for participants and mentors.
Evaluation - 2
- 2nd round evaluation of Track – 1 teams
Valedictory & Prize Distribution
- Closing ceremony
“Design” refers to the software design, development and implementation of the solution on the required development board, including hardware–software integration, testing and optimization.
Prizes & Certificates
Recognizing outstanding hardware innovations and technical achievements at the Edge AI Hackathon 2026
₹45,000 Prize Pool
Exciting cash rewards and certificates of merit for top-performing track winners.
Participant Certificates
All participating teams that successfully submit their solutions and abstracts will receive official participation certificates.
Sponsor Hardware Access
Access to industry-grade hardware development kits and potential perks from sponsors: AMD, Renesas & Microchip.
NEW: Winners of all 3 tracks will additionally receive a Renesas QuickConnect Beginners Kit V2.0, sponsored by Renesas Electronics.
Problem Statements
Explore challenges across 6 different domains.
The official problem statements list for the Edge AI Hackathon 2026 is now live. Analyze the statements, select your track, download the booklets, and build your prototypes.
View Problem StatementsOfficial Links Portal
Quick access to all templates, guidelines, booklets, and files for the Edge AI Hackathon 2026
Confirmation for Selected Finalist Teams
Teams selected for the Final Round must complete their registration and confirmation by 23 September 2026. The registration fee covers full food and accommodation for the onsite Final Round at PMEC.
Note: The registration fee is per participant, not per team. Each team must make one combined payment for all team members.
Final Round Registration (Finalists Only)
CLOSES 23 SEPTExclusive registration form for shortlisted finalist teams. Sent directly via registered email on 18 September 2026.
NOC (No Objection Certificate) Format
Download and print the official NOC template required from your college/department.
Official Participant Guidelines
Important instructions, lab rules, code of conduct, and submission requirements for finalist teams.
Problem Statements Portal
Explore the 36 problem statements mapped across 6 key domains and 3 hardware tracks.
Official Hackathon Brochure
View/download the full booklet covering domains, timeline, guidelines, and rules.
40:60 Evaluation Criteria
Review the track-specific hardware parameters (40%) and general core parameters (60%) weightages.
Sponsorship Packages & Partnership
Explore monetary tiers, in-kind hardware support, and collaborative sponsorship opportunities.
Event Overview & Guidelines
Browse general rules, evaluation criteria, hardware tracks, and coordinator contacts.
OFFICIAL CORRESPONDENCE
For Queries
Frequently Asked Questions
Yes! Finalist teams from leading institutions across India have been shortlisted for the Final Round of IEEE Edge AI Hackathon 2026. You can browse the complete list of teams, team leaders, and institutions in the Finalist Teams section on this portal.
Teams selected for the Final Round will receive their exclusive registration form directly through registered email on 18 September 2026. Finalist teams must complete their registration and confirmation by 23 September 2026. The registration fee is ₹1,200/- per participant for Non-IEEE members and ₹1,000/- per participant for IEEE members, which includes food and accommodation for the onsite Final Round at PMEC. Note: The fee is per participant, and each team should submit one combined payment.
The hackathon is open to B.Tech, M.Tech, and PhD students. Participation must be in teams of 3 to 5 members. Only intra-college teams are allowed (inter-college teams are not permitted), though a team may contain members from different branches or degree streams.
Yes, all participating teams that successfully submit their solutions and abstracts will receive official participation certificates. Winners of the respective tracks (FPGA, Raspberry Pi/Renesas, and ESP/Arduino) will receive certificates of merit alongside cash prizes from the ₹45,000 prize pool.
Development boards (including Microchip PolarFire SoC Discovery Kits, AMD/Xilinx FPGA boards, Raspberry Pi, ESP32, and Renesas kits) will be provided to the qualified teams by the organizers. However, teams must bring their own sensors, actuators, modules, and other peripherals required for their specific project implementations.
Yes! Students from all academic years (including first-year students) and branches are highly encouraged to participate and collaborate on hardware prototyping solutions.
Projects are graded according to the official 40:60 Evaluation Rule. 40% of the score depends on your specific hardware track optimizations (FPGA, Raspberry Pi/Renesas, or ESP32/Arduino). The remaining 60% of the score is based on core factors like innovation, complexity, functionality, track-specific performance, and documentation. You can view the full breakdown of parameters in our Evaluation Criteria Portal.
Organizers & Partners
Collaborating organizations backing the Edge AI Hackathon 2026
Organizers
IEEE Electron Devices Society PMEC SBC
Organizer
IEEE Council on Electronic Design Automation
OrganizerPrincipal Sponsor
AMD
PRINCIPAL SPONSORSponsors
IEEE Bhubaneswar Section
Sponsor
Chips to Start-up (C2S)
Sponsor
ETIOS Society
Sponsor
Dept. of Electronics & Telecommunication Engineering, PMEC
SponsorTechnical Sponsors
Renesas
Technical Sponsor
Microchip
Technical SponsorHosting Partner
Partner With IEEE Edge AI Hackathon 2026
Support student innovation, showcase your brand, and connect with top engineering talent across India.
Explore Sponsorship PackagesInterested in Edge AI 2026?
Stay tuned
Venue & Location
Find your way to the Edge AI Hackathon 2026
Final Merit List
IEEE EDGE AI HACKATHON 2026
Celebrating innovation, engineering excellence, and the achievements of participating teams.
FPGA
Advanced Reconfigurable HardwareRaspberry Pi / Renesas
Edge Computing & SBC InnovationESP32 / Arduino
Embedded IoT & Smart Devices"Scores don’t define engineers; curiosity, persistence, and the courage to build do. Wear your finalist badge with immense pride — the future of Edge AI and Semiconductor innovation belongs to you."
About the Merit List
This merit list reflects the official final rankings of teams who participated in the IEEE EDGE AI HACKATHON 2026, held at PMEC (Parala Maharaja Engineering College), Berhampur, Odisha, on 4–6 October 2026.
Rankings were determined by a panel of expert judges based on technical implementation, innovation, real-world impact, presentation quality, and system completeness.
Marks, scores, percentages, and individual judging breakdowns are not published in compliance with institutional privacy guidelines. Only rank and team name are displayed.
Need Help?
Contact the Organizers
Have queries regarding registration, travel, accommodation, schedule, or hardware? Reach out directly to our organizing team.