Edge AI Hackathon 2026
Join the hardware-centric design revolution. Innovate at the edge, design low-power solutions, and implement machine learning applications on modern embedded systems at Parala Maharaja Engineering College.
Organized by:
- Organizer: IEEE Electron Devices Society PMEC SBC & IEEE Council on Electronic Design Automation.
- Sponsors: IEEE Bhubaneswar Section, Chips to Start-up (C2S), ETIOS Society & Dept. Of Electronics and Telecommunication Engineering.
- Technical Sponsors: AMD, Renesas & Microchip
Event Information
| Event Name: | Edge AI Hackathon 2026 |
| Status: | Round 0 (ongoing) |
| Submission Fee: | ₹0 (100% FREE) Round 0 |
| Abstract Deadline: | |
| Mode: | Offline |
| Venue: | Parala Maharaja Engineering College, Berhampur, Odisha |
| Date: | 4th, 5th, 6th October, 2026 |
| Registration: | Register Now ↗ |
About the Hackathon
The Edge AI Hackathon 2026 is an elite hardware-centric sprint designed to foster local engineering innovation. Participating teams will work under time constraints to address real-world application challenges, creating optimized hardware solutions that utilize embedded intelligence at the sensor node.
By combining FPGA, microcontrollers, and low-latency computer logic, students are encouraged to bridge the gap between high-level algorithms and resource-constrained silicon platforms.
Major Focus Themes:
Microchip PolarFire SoC Discovery Kit joins Edge AI Hackathon 2026
We are excited to announce the addition of the Microchip PolarFire SoC Discovery Kit, powered by the MPFS095T SoC FPGA, to the hardware platforms available for the IEEE Edge AI Hackathon 2026.
This addition expands the hardware ecosystem of the hackathon and gives participating teams another platform for developing innovative solutions in Edge AI, FPGA, Embedded Systems, and hardware acceleration.
Participants can now explore the capabilities of the PolarFire SoC platform as part of their hackathon development journey.
PolarFire® SoC
MPFS095T SoC FPGA
About Parala Maharaja Engineering College (PMEC)
Parala Maharaja Engineering College (PMEC), Berhampur came into existence in the year 2009 on April 26th, with an area of nearly 80 acres. Now this college acts as an Autonomous college affiliated to BPUT, Odisha, from the year 2021. This college is one of the premier technical institutes in the state and is the only Government Engineering College in South Odisha. It offers 8 B.Tech programmes, 5 M.Tech programmes, and serves as a Nodal Centre for Ph.D. research under BPUT.
Government of Odisha has recognized PMEC as a leading institution with state-of-the-art academic infrastructure, laboratories, library, hostels, research facilities and continuous campus development.
Department of Electronics & Telecommunication Engineering
The Department of Electronics and Telecommunication Engineering was established in 2013 with an intake of 60 students. The department has expertise in Communication Systems, Image Processing, Signal Processing, VLSI Design and Embedded Systems.
Students receive extensive laboratory exposure through modern facilities and project-based learning. The department has received ₹65.19 Lakhs under the Chips-to-Startup (C2S) scheme from MeitY, Government of India, enabling the establishment of advanced laboratories equipped with industry-standard FPGA boards and EDA software. Graduates pursue successful careers in both core electronics and IT industries.
Chips to Startup (C2S) Programme
National Semiconductor Initiative • Ministry of Electronics & Information Technology (MeitY) • Government of India
Parala Maharaja Engineering College (PMEC) is proudly selected under the national C2S Programme to foster indigenous chip design capabilities.
About C2S
A national initiative by MeitY to catalyze the domestic semiconductor ecosystem. The programme empowers engineering institutions with advanced training in Chip Design, FPGA, ASIC, and SoC development. Supported by a ₹65.19 lakh grant, PMEC bridges theoretical VLSI concepts with real-world silicon innovation through the state-of-the-art EDCSD Laboratory.
PMEC's Indigenous Chip
IC-C2S0061
A High-Performance Multiplier IC designed entirely by researchers at PMEC and presented under the national C2S Programme. Fabricated through SCL Chandigarh, it stands as one of India's indigenous semiconductor chips powering modern hardware applications.
IEEE Community at PMEC
A growing ecosystem of IEEE student professionals, researchers, and innovators at Parala Maharaja Engineering College
IEEE Student Branch PMEC
Established in November 2024, the IEEE Student Branch at PMEC is one of the fastest-growing student communities in Odisha, promoting innovation through workshops, competitions, technical talks, and industry interaction.
IEEE Electron Devices Society PMEC SBC
Established in April 2026, the IEEE EDS Student Branch Chapter focuses on semiconductor devices, VLSI, embedded systems, Edge AI, and hardware innovation through research, hackathons, and technical activities.
IEEE Council on Electronic Design Automation
The IEEE CEDA chapter promotes Electronic Design Automation, FPGA, ASIC, SoC design, and hardware innovation while supporting the Chips to Startup (C2S) ecosystem at PMEC.
Faculty Leadership
Dr. Raghunandan Swain
Providing academic leadership and research guidance to the IEEE EDS PMEC Student Branch Chapter, fostering innovation in semiconductor devices, VLSI, and embedded systems.
View Profile
Dr. Suryalok Dash
Mentoring IEEE student activities and fostering professional growth through technical and leadership initiatives across the IEEE Student Branch and EDS Chapter.
View ProfileWhy Build at PMEC?
Unlocking potential through state-of-the-art silicon design labs and advanced embedded systems platforms
Advanced FPGA Laboratory
Access high-end AMD/Xilinx FPGA boards for real-time parallel computing and custom logic hardware design.
Industry Standard EDA Tools
Train on professional Electronic Design Automation software suites for schematic entry, circuit simulation, and layout design.
Renesas & AMD Hardware
Prototype on modern Edge AI hardware platforms, including Renesas microcontrollers and AMD system-on-chips.
Embedded Systems Development
Deploy low-power algorithms onto ARM Cortex and RISC-V development architectures using multi-sensor interfaces.
C2S Semiconductor Laboratory
Leverage the MeitY-backed Chips-to-Startup laboratory ecosystem designed specifically for microelectronics and chip design.
Research Driven Environment
Collaborate under academic mentors specializing in VLSI circuits, machine learning acceleration, and smart sensor nodes.
Supported Hardware Platforms
Explore the diverse suite of FPGA, microcontroller, and edge compute platforms available to hackathon teams
Microchip
Microchip PolarFire SoC Discovery Kit
Features a multi-core RISC-V Linux-capable processor subsystem integrated with a low-power PolarFire FPGA fabric, ideal for real-time Edge AI vision, signal processing, and low-latency hardware acceleration.
- Quad-core 64-bit RV64GC RISC-V CPU
- 95K Low-power Logic Elements
- Linux OS & Bare-metal Support
AMD
AMD / Xilinx FPGA Development Boards
High-throughput FPGA architectures engineered for custom hardware logic synthesis, DSP arithmetic pipelines, high-speed interfaces, and parallel matrix compute acceleration.
- High-density DSP slices & Block RAM
- Vivado ML EDA Toolchain suite
- Real-time parallel algorithmic pipelining
Renesas
Renesas Edge AI Development Kits
Ultra-low power, security-enabled microcontroller evaluation boards tailored for deploying machine learning inference models at the sensor edge with energy efficiency.
- Hardware-accelerated neural compute units
- Flexible Software Package (FSP)
- Low-power deep sleep operating modes
Raspberry Pi 4 / 5 Compute Platforms
Versatile embedded Linux single-board computers optimized for real-time video analytics, sensor hub fusion, Python/TensorFlow Lite deployment, and edge gateway solutions.
- TensorFlow Lite / ONNX / OpenCV
- CSI Camera & multi-sensor buses
- High-speed Gigabit networking
ESP32 Intelligent Embedded Modules
Cost-effective, highly integrated Wi-Fi and Bluetooth SoC modules engineered for TinyML applications, edge telemetry, distributed sensor networks, and low-power control.
- TinyML & Edge Impulse integration
- Ultra-low sleep current operations
- Wireless mesh & cloud connectivity
Event Timeline
Round 0 (Abstract Submission)
FREE SUBMISSIONRound 0 (Result Announcement)
September 18, 2026Round 1 (Software Simulation - Online)
Sept 18 - Oct 04, 2026Round 2 (Hardware Implementation - On Site)
Oct 04 - Oct 06, 2026Eligibility Criteria
-
Open to all Degree Students
Students from any degree can participate i.e., B.Tech, M.Tech, PhD.
-
Individual / Team Participation
Register as a team to collaborate on hardware and software implementation tracks.
-
Maximum Team Size: 5 Members
Teams must contain 3 to 5 members to distribute work across architecture, programming and hardware implementation.
-
All Branches are Welcomed
No restriction on departments—ECE, CSE, EE, and ME branches can form multidisciplinary teams.
Prizes & Certificates
Recognizing outstanding hardware innovations and technical achievements at the Edge AI Hackathon 2026
₹45,000 Prize Pool
Exciting cash rewards and certificates of merit for top-performing track winners.
Participant Certificates
All participating teams that successfully submit their solutions and abstracts will receive official participation certificates.
Sponsor Hardware Access
Access to industry-grade hardware development kits and potential perks from sponsors: AMD, Renesas & Microchip.
Problem Statements
Explore challenges across 6 different domains.
The official problem statements list for the Edge AI Hackathon 2026 is now live. Analyze the statements, select your track, download the booklets, and build your prototypes.
View Problem StatementsOfficial Links Portal
Quick access to all templates, registration forms, booklets, and files for the Edge AI Hackathon 2026
Abstract Submission Format (Round 0)
Download/copy the official template to structure your project proposal abstract.
Registration Form (All Tracks)
FREE SUBMISSIONOfficial registration form to submit your abstract and select hardware tracks. ₹0 Submission Fee for Round 0.
Official Hackathon Brochure
View/download the full booklet covering domains, timeline, guidelines, and rules.
Problem Statements Portal
Explore the 36 problem statements mapped across 6 key domains and 3 hardware tracks.
40:60 Evaluation Criteria
Review the track-specific hardware parameters (40%) and general core parameters (60%) weightages.
Event Overview & Guidelines
Browse general rules, evaluation criteria, hardware tracks, and coordinator contacts.
Shortlisted Teams Registration Link
Registration link for teams selected for Round 1 & Round 2. To be shared after abstract results.
OFFICIAL CORRESPONDENCE
For Queries
Frequently Asked Questions
Online registration forms are active and completely free (₹0 submission fee for Round 0). Click here to Register
Now ↗ and submit your project proposal abstract before the Round 0 (Abstract Submission)
extended deadline on 15 September 2026 (15 August 2026).
The hackathon is open to B.Tech, M.Tech, and PhD students. Participation must be in teams of 3 to 5 members. Only intra-college teams are allowed (inter-college teams are not permitted), though a team may contain members from different branches or degree streams.
Yes, all participating teams that successfully submit their solutions and abstracts will receive official participation certificates. Winners of the respective tracks (FPGA, Raspberry Pi/Renesas, and ESP/Arduino) will receive certificates of merit alongside cash prizes from the ₹45,000 prize pool.
Development boards (including Microchip PolarFire SoC Discovery Kits, AMD/Xilinx FPGA boards, Raspberry Pi, ESP32, and Renesas kits) will be provided to the qualified teams by the organizers. However, teams must bring their own sensors, actuators, modules, and other peripherals required for their specific project implementations.
Yes! Students from all academic years (including first-year students) and branches are highly encouraged to participate and collaborate on hardware prototyping solutions.
Projects are graded according to the official 40:60 Evaluation Rule. 40% of the score depends on your specific hardware track optimizations (FPGA, Raspberry Pi/Renesas, or ESP32/Arduino). The remaining 60% of the score is based on core factors like innovation, complexity, functionality, track-specific performance, and documentation. You can view the full breakdown of parameters in our Evaluation Criteria Portal.
Organizers & Partners
Collaborating organizations backing the Edge AI Hackathon 2026
Organizers
IEEE Electron Devices Society PMEC SBC
Organizer
IEEE Council on Electronic Design Automation
OrganizerSponsors
IEEE Bhubaneswar Section
Sponsor
Chips to Start-up (C2S)
Sponsor
ETIOS Society
Sponsor
Dept. of Electronics & Telecommunication Engineering, PMEC
SponsorTechnical Sponsors
AMD
Technical Sponsor
Renesas
Technical Sponsor
Microchip
Technical SponsorInterested in Edge AI 2026?
Stay tuned
Venue & Location
Find your way to the Edge AI Hackathon 2026