Official Problem Statements
Choose your challenge. Build the future.
36
Total Statements
6
Problem Domains
3
Hardware Tracks
₹45,000
Total Prize Pool
Download Complete Problem Statement Document
Download the official Edge AI Hackathon 2026 Problem Statement Booklet containing all domains, tracks and evaluation criteria.
Problem Statements Database
Search and filter statements dynamically to find the perfect project for your team.
| Sl. No. | Domain | PS No. | Problem Statement | Description |
|---|
Hardware Tracks
Select your track and check its evaluation parameters below.
FPGA & SoC FPGA Track
Hardware Design & Optimization
Implement parallel structures, pipelining, and optimization algorithms on FPGA & SoC FPGA platforms (AMD/Xilinx & Microchip PolarFire SoC).
View CriteriaRaspberry Pi / Renesas
Embedded Edge Computing
Deploy TinyML models, real-time filters, and processing codes directly at the edge.
View CriteriaESP32 / Arduino
Intelligent Embedded Systems
Design low-power, efficient system nodes and sensors networks for on-device compute.
View CriteriaTrack Specifics (40% Weightage)
- Hardware Resource Utilization: Efficient use of LUTs, Flip-Flops, DSPs, BRAMs, and routing resources.
- Latency: Processing cycle overhead from sample inputs to outputs.
- Throughput: Data bytes or execution counts processed per unit time.
- Power Efficiency: Overall operating power levels for execution.
- Hardware Parallelism: Utilization of pipelined arithmetic, parallel structures, and SIMD principles.
- Timing Performance: Ability to satisfy timing constraints and clock boundaries without hazards.
- Scalability: Expandable design structures for broader datasets.
- System Integration: Interfacing with external displays, memories, cameras, or ADCs.
- Real-Time Performance: Latency thresholds and runtime responsiveness.
- Edge Intelligence: Efficient execution of calculations on-device without network lookups.
- System Reliability: Steady execution, memory leaks handling, and backup safety routines.
- Resource Optimization: System parameters checks for CPU, system memory, and memory buffers.
- Power Efficiency: Optimized runtime clock management for energy conservation.
- Peripheral Integration: Interfacing with actuators, networking modules, and high-frequency sensors.
- Software Architecture: Logical software hierarchies, clean structural divisions, and comments.
- Scalability & Deployment: Adaptability for field testing and packaging.
- Embedded System Design: Efficient codes fitting low-resource environments.
- Real-Time Response: Interruption loops handling and immediate sensor registers updates.
- Power Consumption: Deep-sleep optimization and low battery operating limits.
- Sensor & Peripheral Integration: Proper utilization of SPI, I2C, and UART registers.
- Communication Reliability: Consistent network packet relays over Wi-Fi, BLE, or LoRa.
- Code Efficiency: RAM/Flash footprint reduction and modular structures.
- Practical Deployment: Structural sturdiness, user UI accessibility, and design usability.
- Cost Effectiveness: Cost margins for overall components selection.
Evaluation Weightage Scheme
⚖️ The 40:60 Evaluation Rule
Every project's final score is calculated using a dual weightage scheme:
• 40% Weightage goes to your chosen hardware track design & optimizations (FPGA, Rpi/Renesas, or ESP32/Arduino parameters on the left).
• 60% Weightage goes to the general parameters listed below:
| Evaluation Parameter | Weightage |
|---|---|
| Innovation & Originality | 20% |
| Technical Complexity | 15% |
| Functionality & Demonstration | 20% |
| Track-Specific Technical Performance | 30% |
| Presentation & Documentation | 15% |
Need Clarifications?
If you have any questions regarding the problem statements, track compatibility, or hardware constraints, reach out directly to the IEEE EDS PMEC student branch organizers.